Silicon epitaxy devices are built on the top silicon layer of a semiconductor wafer. The yield for such devices generally is lower in portions of the wafer where the electrical resistivity of the top silicon layer is less than certain limits, particularly if the resistivity drops off abruptly. For example, the electrical resistivity typically has been seen to drop off in the region near the wafer edge. One reason that the yield may be reduced is that the lower resistivity results in a lower breakdown voltage, which reduces the yield for all types of devices and particularly for power devices.
The electrical resistivity generally reduces towards the edge of the wafer because of, among other phenomenon, autodoping. Autodoping is the reintroduction of dopant atoms into the semiconductor surface, which causes variations in dopant concentration and may reduce electrical resistivity at the surface. Autodoping can be controlled by adjusting various process parameters.
Yield per wafer improves as more of the total surface area of the wafer can reliably be used to build devices. Therefore, it is desirable to build devices throughout the wafer surface, including as close as possible to the wafer edge.